This invention relates to temperature control systems which maintain the temperature of an electronic device near a constant set point temperature while the device is being tested; and it relates to subassemblies which comprise key portions of such temperature control systems.
Two specific examples of electronic devices which have a need to be tested near a constant temperature are packaged integrated chips, or bare chips which are unpackaged. Any type of circuitry can be integrated into the chips, such as digital logic circuitry or memory circuitry or analog circuitry. Also, the circuitry in the chips can be comprised of any type of transistors, such as field effect transistors or bipolar transistors.
One reason for trying to keep the temperature of a chip constant while it is tested is that the speed with which the chip operates may be temperature dependent. For example, a chip comprised of complementary field effect transistors (CMOS transistors) typically increases its speed of operation by about 0.3% per .degree. C. drop in chip temperature.
A common practice in the chip industry is to mass produce a particular type of chip, and then speed sort them and sell the faster operating chips at a higher price. CMOS memory chips and CMOS microprocessor chips are processed in this fashion. However, in order to determine the speed of such chips properly, the temperature of each chip must be kept nearly constant while the speed test is performed.
Maintaining the chip temperature near a constant set point is quite simple if the instantaneous power dissipation of the chip is constant or varies in a small range while the speed test is being performed. In that case, it is only necessary to couple the chip through a fixed thermal resistance to a thermal mass which is at a fixed temperature. For example, if the maximum chip power variation is ten watts, and the coupling between the chip and the thermal mass is 0.2.degree. C./watt, then the chip temperature will vary a maximum of 2.degree. C.
But, if the instantaneous power dissipation of the chip varies up and down in a wide range while the speed test is being performed, then maintaining the chip temperature near a constant set point is very difficult. Each time the device power dissipation makes a big change, its temperature and its speed will also make a big change.
The above problem is particularly severe in CMOS chips because their instantaneous power dissipation increases as the number of CMOS transistors which are switching ON or OFF increases. During the speed test of a CMOS chip, the number of transistors which are switching is always changing; thus, the chip's power dissipation and temperature and speed are always changing. Also, the magnitude of these changes increases as more transistors get integrated into a single chip, because the number of transistors which are switching at any particular instant will vary from none to all of the transistors on the chip.
In the prior art, several temperature control systems for integrated circuit chips have been disclosed by the following U.S. Pat. Nos.:
______________________________________ 5,420,521 5,297,621 5,104,661 5,315,240 5,205,132 5,125,656 5,309,090 5,172,049 4,734,872. ______________________________________
However, none of the temperature control systems which are disclosed in the above patents are capable of enabling speed tests to be run on chips which widely vary their power dissipation during the test. This is because the above temperature control systems cannot react fast enough to compensate for such instantaneous power variations.
In the above patent '656 and '661 and '090 and '240, no means are provided for removing heat from the chip; they merely include various heaters for adding heat to the chip. These control systems are suitable only for raising the chip's temperature to an elevated level, such as above 200.degree. C., at which "burn-in" tests are performed. At any elevated temperature, the failure of weak or faulty components in a chip is accelerated, and the "burn-in" test causes such components to fail after several hours.
In the above patents '872 and '132 and '621, the chip temperature is increased or lowered by directing a temperature controlled gas jet at the chip or immersing the chip in a temperature controlled liquid. But, these control systems are limited by the speed at which the temperature of the gas jet or liquid can be increased or decreased.
In patent '521, a control system is disclosed in FIG. 7 which includes both a heater for heating the chip and a liquid cooled aluminum block for cooling the chip. However, the FIG. 7 control system still is not capable of enabling speed tests to be run on chips which widely vary their power dissipation during the test, because it cannot react fast enough to compensate for such power variations. Why this deficiency occurs is explained herein in detail in conjunction with FIGS. 8, 9, and 10.
Accordingly, a primary object of the inventions which are disclosed herein is to provide novel temperature control systems, and novel subassemblies for such systems, which react quickly to large variations in power dissipation within an electronic device and thereby maintain the device temperature near a constant set point temperature while the device is being tested.